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3 V LVDS Quad CMOS Differential Line Driver ADN4667
FEATURES
15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 V power supply 310 mV differential signaling Low power dissipation (10 mW typical) Interoperable with existing 5 V LVDS receivers High impedance on LVDS outputs on power-down Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range: -40C to +85C Available in low profile TSSOP package
FUNCTIONAL BLOCK DIAGRAM
VCC
ADN4667
DIN1
D1
DOUT1+ DOUT1- DOUT2+ DOUT2- DOUT3+ DOUT3- DOUT4+ DOUT4-
07032-001
DIN2
D2
DIN3
D3
DIN4 EN EN GND
D4
APPLICATIONS
Backplane data transmission Cable data transmission Clock distribution
Figure 1.
GENERAL DESCRIPTION
The ADN4667 is a quad, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically 3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typically 310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver. The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW. The ADN4667 and a companion LVDS receiver offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADN4667 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 4 Test Circuits ....................................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 11 Enable Inputs .............................................................................. 11 Applications Information .......................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
1/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4667 SPECIFICATIONS
VCC = 3.0 V to 3.6 V; RL = 100 ; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.1 Table 1.
Parameter Min 250 1.125 Typ 310 1 1.17 1 1.33 1.02 Max 450 35 1.375 25 1.6 Unit mV |mV| V |mV| V V V V A A V mA mA A A Conditions/Comments2, 3 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4
LVDS OUTPUTS (DOUT+, DOUT-)
Differential Output Voltage, VOD Change in Magnitude of VOD for Complementary Output States, VOD Offset Voltage, VOS Change in Magnitude of VOS for Complementary Output States, VOS Output High Voltage, VOH Output Low Voltage, VOL
0.90 2.0 GND -10 -10 -1.5
INPUTS (DIN, EN, EN)
Input High Voltage, VIH Input Low Voltage, VIL Input High Current, IIH Input Low Current, IIL Input Clamp Voltage, VCL VCC 0.8 +10 +10
+2 +2 -0.8 -4.2 -4.2
VIN = VCC or 2.5 V VIN = GND or 0.4 V ICL = -18 mA Enabled, DIN = VCC, DOUT+ = 0 V or DIN = GND, DOUT- = 0 V Enabled, VOD = 0 V VOUT = 0 V or 3.6 V, VCC = 0 V or open EN = 0.8 V and EN = 2.0 V, VOUT = 0 V or VCC DIN = VCC or GND RL = 100 all channels, DIN = VCC or GND (all inputs) DIN = VCC or GND, EN = GND, EN = VCC Human body model Human body model
LVDS OUTPUT PROTECTION (DOUT+, DOUT-)
Output Short-Circuit Current, IOS4 Differential Output Short-Circuit Current, IOSD4 -9.0 -9.0 +20 +10
LVDS OUTPUT LEAKAGE (DOUT+, DOUT-)
Power-Off Leakage, IOFF Output Three-State Current, IOZ -20 -10 1 1
POWER SUPPLY
No Load Supply Current, Drivers Enabled, ICC Loaded Supply Current, Drivers Enabled, ICCL No Load Supply Current, Drivers Disabled, ICCZ 4.0 20 2.2 15 4 8.0 30 6.0 mA mA mA kV kV
ESD PROTECTION
DOUT+, DOUT- Pins All Pins Except DOUT+, DOUT-
1 2
All typical values are given for VCC = +3.3 V, TA = +25C. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD VOD, and VOS. 3 The ADN4667 is a current-mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 to 110 . 4 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Rev. 0 | Page 3 of 12
ADN4667
AC CHARACTERISTICS 1
VCC = 3.0 V to 3.6 V; RL = 100 ; CL 2 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. 3 Table 2.
Parameter Differential Propagation Delay, High to Low, tPHLD Differential Propagation Delay, Low to High, tPLHD Differential Pulse Skew |tPHLD - tPLHD|, tSKD1 6 Channel-to-Channel Skew, tSKD2 7 Differential Part-to-Part Skew, tSKD3 8 Differential Part-to-Part Skew, tSKD4 9 Rise Time, tTLH Fall Time, tTHL Disable Time High to Inactive, tPHZ Disable Time Low to Inactive, tPLZ Enable Time Inactive to High, tPZH Enable Time Inactive to Low, tPZL Maximum Operating Frequency, fMAX 10
1 2 3
Min 0.5 0.5 0 0 0 0
Typ 0.9 1.2 0.3 0.4
200
0.5 0.5 2 2 3 3 250
Max 1.7 1.7 0.4 0.5 1.0 1.2 1.5 1.5 5 5 7 7
Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz
Conditions/Comments 4, 5 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6
AC parameters are guaranteed by design and characterization. CL includes probe and jig capacitance. All typical values are given for VCC = +3.3 V, TA = +25C. 4 Generator waveform for all tests unless otherwise specified: f = 50 MHz, ZO = 50 , tr 1 ns, and tf 1 ns. 5 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. 6 tSKD1 = |tPHLD - tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 7 tSKD2 is the differential channel-to-channel skew of any event on the same device. 8 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. 9 tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max - Min| differential propagation delay. 10 fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels switching.
Rev. 0 | Page 4 of 12
ADN4667 TEST CIRCUITS
VCC DOUT+ CL SIGNAL GENERATOR DIN DOUT- CL
DOUT+ VCC DIN RL/2
V VOS V VOD
07032-002
50
RL/2 DOUT-
DRIVER IS ENABLED
NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
Figure 2. Test Circuit for Driver VOD and VOS
Figure 3. Test Circuit for Driver Propagation Delay and Transition Time
3V
DIN
1.5V 0V
tPLHD
DOUT- DOUT+
VOD
tPHLD
VOH 0V (DIFFERENTIAL) VOL
VDIFF VDIFF = DOUT+ - DOUT-
80% 0V 20%
07032-004
tTLH
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
DOUT+ CL
50 50 1.2V
VCC
DIN CL
DOUT-
EN
SIGNAL GENERATOR
50
EN
Figure 5. Test Circuit for Driver Three-State Delay
3V EN WITH EN = GND OR OPEN-CIRCUIT 1.5V 0V 3V EN WITH EN = VCC 1.5V 0V
tPHZ
DOUT+ WITH DIN = VCC OR DOUT- WITH DIN = GND
tPZH
50%
VOH
1.2V 1.2V DOUT+ WITH DIN = GND OR DOUT- WITH DIN = VCC 50%
Figure 6. Driver Three-State Delay Waveforms
Rev. 0 | Page 5 of 12
07032-006
tPLZ
tPZL
VOL
07032-005
07032-003
DRIVER IS ENABLED
ADN4667 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VCC to GND Input Voltage (DIN) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (DOUT+, DOUT-) to GND Short-Circuit Duration (DOUT+, DOUT-) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation TSSOP Package JA Thermal Impedance Reflow Soldering Peak Temperature (10 sec) Rating -0.3 V to +4 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V Continuous -40C to +85C -65C to +150C 150C (TJ max - TA)/JA 150.4C/W 260C max
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 12
ADN4667 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1 DIN1 2 DIN2 3 VCC 4 GND 5 DIN3 6 DIN4 7 EN 8
16 DOUT1- 15 DOUT1+
ADN4667
TOP VIEW (Not to Scale)
14 DOUT2+ 13 DOUT2- 12 DOUT3- 11 DOUT3+ 10 DOUT4+ 9
DOUT4-
07032-007
NC = NO CONNECT
Figure 7. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic EN DIN1 DIN2 VCC GND DIN3 DIN4 EN DOUT4- DOUT4+ DOUT3+ DOUT3- DOUT2- DOUT2+ DOUT1+ DOUT1- Description Active High Enable and Power-Down Input (3 V TTL/CMOS). If EN is held low or open-circuit, EN enables the drivers when high and disables the drivers when low. Driver Channel 1 Logic Input. Driver Channel 2 Logic Input. Power Supply Input. These parts can be operated from 3.0 V to 3.6 V; and the supply should be decoupled with a 10 F solid tantalum capacitor in parallel with a 0.1 F capacitor to GND. Ground Reference Point for All Circuitry on the Part. Driver Channel 3 Logic Input. Driver Channel 4 Logic Input. Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). If EN is held high, EN enables the drivers when low or open-circuit and disables the drivers and powers down the device when high. Channel 4 Inverting Output Current Driver. When DIN4 is high, current flows into DOUT4-; when DIN4 is low, current flows out of DOUT4-. Channel 4 Noninverting Output Current Driver. When DIN4 is high, current flows out of DOUT4+; when DIN4 is low, current flows into DOUT4+. Channel 3 Noninverting Output Current Driver. When DIN3 is high, current flows out of DOUT3+; when DIN3 is low, current flows into DOUT3+. Channel 3 Inverting Output Current Driver. When DIN3 is high, current flows into DOUT3-; when DIN3 is low, current flows out of DOUT3-. Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2-; when DIN2 is low, current flows out of DOUT2-. Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+; when DIN2 is low, current flows into DOUT2+. Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+; when DIN1 is low, current flows into DOUT1+. Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1-; when DIN1 is low, current flows out of DOUT1-.
Rev. 0 | Page 7 of 12
ADN4667 TYPICAL PERFORMANCE CHARACTERISTICS
1.415
OUTPUT THREE-STATE CURRENT, IOZ (pA)
TA = 25C RL = 100
440
TA = 25C VIN = GND OR VCC
OUTPUT HIGH VOLTAGE, VOH (V)
420
1.414
400
380
1.413
360
07032-011
07032-008
1.412 3.0
3.1
3.2
3.3
3.4
3.5
3.6
340 3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 8. Output High Voltage vs. Power Supply Voltage
1.090
Figure 11. Output Three-State Current vs. Power Supply Voltage
325.0
DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
TA = 25C RL = 100
TA = 25C RL = 100
OUTPUT LOW VOLTAGE, VOL (V)
324.8
1.089
324.6
324.4
1.088
324.2
07032-012
07032-009
1.087 3.0
3.1
3.2
3.3
3.4
3.5
3.6
324.0 3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 9. Output Low Voltage vs. Power Supply Voltage
-3.9
Figure 12. Differential Output Voltage vs. Power Supply Voltage
500
DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV)
SHORT-CIRCUIT CURRENT, I OS (mA)
TA = 25C VIN = GND OR VCC VOUT = 0V
TA = 25C VCC = 3.3V
450
-4.0
400
350
-4.1
300
07032-013
07032-010
-4.2 3.0
3.1
3.2
3.3
3.4
3.5
3.6
250 90
100
110
120
130
140
150
POWER SUPPLY VOLTAGE, VCC (V)
LOAD RESISTOR, RL ()
Figure 10. Output Short-Circuit Current vs. Power Supply Voltage
Figure 13. Differential Output Voltage vs. Load Resistor
Rev. 0 | Page 8 of 12
ADN4667
1.252 TA = 25C RL = 100 14.92
POWER SUPPLY CURRENT, ICC (mA)
OFFSET VOLTAGE, VOS (mV)
14.91
1.251
14.90
1.250
14.89
07032-014
1.249 3.0
3.1
3.2
3.3
3.4
3.5
3.6
14.88 -40
-20
0
20
40
60
80
100
POWER SUPPLY VOLTAGE, VCC (V)
AMBIENT TEMPERATURE, TA (C)
Figure 14. Offset Voltage vs. Power Supply Voltage
26
Figure 17. Power Supply Current vs. Ambient Temperature
1200
24
22 ALL CHANNELS SWITCHING 20
DIFFERENTIAL PROPAGATION DELAY (ns)
POWER SUPPLY CURRENT, ICC (mA)
TA = 25C CL = 15pF VCC = 3.3V VIN = 0V TO 3V RL = 100 PER DRIVER
TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER
1100
tPHLD tPLHD
18
1000
16 ONE CHANNEL SWITCHING 14 0.1 1 10 100 500
07032-015
900 3.0
3.1
3.2
3.3
3.4
3.5
3.6
SWITCHING FREQUENCY, f (MHz)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 15.Power Supply Current vs. Switching Frequency
14.925 TA = 25C f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100 PER DRIVER
Figure 18. Differential Propagation Delay vs. Power Supply Voltage
1200 VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER tPLHD 1100
14.920
DIFFERENTIAL PROPAGATION DELAY (ns)
POWER SUPPLY CURRENT, ICC (mA)
tPHLD 1000
14.915
07032-016
14.910 3.0
3.1
3.2
3.3
3.4
3.5
3.6
900 -40
-20
0
20
40
60
80
100
POWER SUPPLY VOLTAGE, VCC (V)
AMBIENT TEMPERATURE, TA (C)
Figure 16. Power Supply Current vs. Power Supply Voltage
Figure 19. Differential Propagation Delay vs. Ambient Temperature
Rev. 0 | Page 9 of 12
07032-019
07032-018
07032-017
VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100 PER DRIVER
ADN4667
100 TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER
TRANSITION TIME (ps)
400
DIFFERENTIAL SKEW, tSKD (ps)
80
TA = 25C f = 1MHz CL = 15pF RL = 100 PER DRIVER tTLH
380
60
360
tTHL
40
20
07032-020
340
07032-022
0 3.0
3.1
3.2
3.3
3.4
3.5
3.6
320 3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 20. Differential Skew vs. Supply Voltage
50 VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER
TRANSITION TIME (ps)
Figure 22. Transition Time vs. Supply Voltage
400 VCC = 3.3V f = 1MHz CL = 15pF RL = 100 PER DRIVER
DIFFERENTIAL SKEW, tSKD (ps)
40
380 tTLH 360 tTHL
30
20
10
07032-021
340
07032-023
0 -40
-20
0
20
40
60
80
100
320 -40
-20
0
20
40
60
80
100
AMBIENT TEMPERATURE, TA (C)
AMBIENT TEMPERATURE, TA (C)
Figure 21. Differential Skew vs. Ambient Temperature
Figure 23. Transition Time vs. Ambient Temperature
Rev. 0 | Page 10 of 12
ADN4667 THEORY OF OPERATION
The ADN4667 is a quad line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted pair cable or PCB backplane, to an LVDS receiver, where it develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 . The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When DIN is high (Logic 1), current flows out of the DOUT+ pin (current source) through RT and back into the DOUT- pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and gives a Logic 1 at the receiver output. When DIN is low, DOUT+ sinks current and DOUT- sources current; a negative differential voltage across RT gives a Logic 0 at the receiver output. The output drive current is between 2.5 mA and 4.5 mA (typically 3.1 mA), developing between 250 mV and 450 mV across a 100 termination resistor. The received voltage is centered around the receiver offset of 1.2 V. In other words, the noninverting receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input is (1.2 V - [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current-mode drivers offer considerable advantages over voltage-mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage-mode drivers increases exponentially in most cases. This is caused by the overlap as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. A current-mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL.
ENABLE INPUTS
The ADN4667 has active high and active low enable inputs, which deactivate all the current drivers when in the disabled state. This also powers down the device and reduces the current consumption from typically 20 mA to typically 2.2 mA. A truth table for the enable inputs is shown in Table 5. Table 5. Enable Inputs Truth Table
EN EN DIN L H X DOUT+ ISINK ISOURCE Inactive DOUT- ISOURCE ISINK Inactive H L or open H L or open Any other combination of EN and EN
APPLICATIONS INFORMATION
Figure 24 shows a typical application for point-to-point data transmission.
1/4 ADN4667 EN EN RECEIVER DOUT
07032-024
DIN
RT 100
Figure 24. Typical Application Circuit
Rev. 0 | Page 11 of 12
ADN4667 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN4667ARUZ1 ADN4667ARUZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option RU-16 RU-16
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07032-0-1/08(0)
Rev. 0 | Page 12 of 12

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